VLSI Chip Design Hands on using open source EDA

Prospective Experts:

• Dr. H. S. Jatana
• Industry support- VLSI System Design Corp
• Prof. Gaurav Trivedi, IIT Guwahati
• Prof. Vineet Sahula, MNITJ

Principal Coordinator :

• Dr. Gaurav Trivedi , IIT Guwahati

16 – 20 Dec 2019

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Local Coordinator:
Dr. Dip Prakash Samajdar
Email:dip.samajdar@iiitdmj.ac.in
Phone: 9477137992
0761-2794474

S.No.

Module Name

Topics

1.

Study various components of RISC-V microprocessor based SoC and review all components using MAGIC Layout tool

• Brief introduction RISC-V ISA
• Overview of RISC-V based micro-processor and its related SoC
• Overview of QFN48 package, pads, macros and memory in MAGIC
• Idea of chip-planning, aspect ratio, utilization factor, power planning, decoupling capacitor, pads/memory and macro placement

2.

Study the importance of standard cell library and design & characterize one cell using MAGIC Layout tool and ngSPICE for SPICE simulations

• Pros and cons of good-bad floorplan
• Introduction to lab to create floorplan for small design, which will be covered in detail on Day 4)
• System-on-Chip (SoC) planning and design concepts overview
• Physical design overview
• Why Libraries are called the soul and heart of semi-conductor industry?
• Standard cells library overview

3.

Pre-layout timing analysis of SoC using OpenSTA, chip planning using MAGIC and block-level placement/routing using qflow RTL2GDS opensource EDA toolchain

• Art of layout – Stick diagram + Euler’s path using MAGIC
• Characterization of important parameters using ngSPICE
• Introduction to 16-Mask CMOS process and its significance to chip design flow
• Logic synthesis and high fanout net synthesis interactive tutorial using Yosys opensource synthesis tool

4.

Hierarchical placement/routing using pads and blocks, and perform sign-off checks viz.
LVS/DRC using Magic

• Introduction to static timing analysis and the related Industry standard reporting formats
• Pre-layout timing analysis of a design using OpenSTA opensource STA tool, which includes setup timing analysis for reg2reg and IO
• Introduction to clock tree synthesis (CTS) and its related checks viz. skew, latency, pulse-width, duty cycle
• Placement/Routing/CTS of a design using qflow opensource RTL2GDS tool

• Perform CTS quality and routing quality checks using OpenSTA

5.

Post-layout timing analysis using OpenSTA and engineering change order (ECO) using Tritonsizer

• Full chip integration using MAGIC for a design with blocks and pads.
• Revise floorplan from Day 2
• Populate layout from library manager in MAGIC, select digital core block and additional pads
• Arrange pads and create a pad-frame hierarchy
• Project work using SiFive E31 RISC-V design blocks