VLSI Chip Design Hands on using open source EDA

Prospective Experts:

  • Dr. H. S. Jatana
  • Industry support- VLSI System Design Corp
  • Prof. Gaurav Trivedi, IIT Guwahati
  • Prof. Vineet Sahula, MNITJ

Principal Coordinator :

  • Dr. Gaurav Trivedi , IIT Guwahati

16 20 Dec 2019

Download Brochure

Apply Online

Local Coordinator:
Dr. Dip Prakash Samajdar
Phone: 9477137992

Course contents:


Module Name



Study various components of RISC-V microprocessor based SoC and review all components using MAGIC Layout tool

  • Brief introduction RISC-V ISA
  • Overview of RISC-V based micro-processor and its related SoC
  • Overview of QFN48 package, pads, macros and memory in MAGIC
  • Idea of chip-planning, aspect ratio, utilization factor, power planning, decoupling capacitor, pads/memory and macro placement


Study the importance of standard cell library and design & characterize one cell using MAGIC Layout tool and ngSPICE for SPICE simulations

  • Pros and cons of good-bad floorplan
  • Introduction to lab to create floorplan for small design, which will be covered in detail on Day 4)
  • System-on-Chip (SoC) planning and design concepts overview
  • Physical design overview
  • Why Libraries are called the soul and heart of semi-conductor industry?
  • Standard cells library overview



Pre-layout timing analysis of SoC using OpenSTA, chip planning using MAGIC and block-level placement/routing using qflow RTL2GDS opensource EDA toolchain

  • Art of layout – Stick diagram + Euler’s path using MAGIC
  • Characterization of important parameters using ngSPICE
  • Introduction to 16-Mask CMOS process and its significance to chip design flow
  • Logic synthesis and high fanout net synthesis interactive tutorial using Yosys opensource synthesis tool


Hierarchical placement/routing using pads and blocks, and perform sign-off checks viz.
LVS/DRC using Magic

  • Introduction to static timing analysis and the related Industry standard reporting formats
  • Pre-layout timing analysis of a design using OpenSTA opensource STA tool, which includes setup timing analysis for reg2reg and IO
  • Introduction to clock tree synthesis (CTS) and its related checks viz. skew, latency, pulse-width, duty cycle
  • Placement/Routing/CTS of a design using qflow opensource RTL2GDS tool
  • Perform CTS quality and routing quality checks using OpenSTA


Post-layout timing analysis using OpenSTA and engineering change order (ECO) using Tritonsizer

  • Full chip integration using MAGIC for a design with blocks and pads.
  • Revise floorplan from Day 2
  • Populate layout from library manager in MAGIC, select digital core block and additional pads
  • Arrange pads and create a pad-frame hierarchy
  • Project work using SiFive E31 RISC-V design blocks

Registration Fee and Accommodation:
No Registration fee is charged for attending this programme planned at any designated academies/Remote centres. However, candidate should submit a Demand Draft/ CBS-Cheque of Rs.1000/- along with application form and the same will be handed over to the participant on the last day of the training. Certificate for participation as well as for Satisfactory performance will be given to the participants subject to fulfillment of attending all sessions, submission of assignments and clearing the test(s).

Boarding and Lodging at Hostels/Guest House will be provided at free of cost only at Identified E&ICT Academies. For details please refer to respective Academy websites. At identified Remote centres only working lunch and snacks will be provided. No Travel Allowance will be paid to the participants.

Core Team Members, E&ICT Academy:

Prof Aparajita Ojha
Email: aojha@iiitdmj.ac.in

Prof. Vijay Kumar Gupta
Email: vkgupta@iiitdmj.ac.in

Prof. P.N. Kondekar
Email: pnkondekar@iiitdmj.ac.in

Dr. Atul Gupta
Email: atul@iiitdmj.ac.in

Dr. Prashant Kumar Jain
Email: pkjain@iiitdmj.ac.in

Website: ict.iiitdmj.ac.in

Contact us :
Maj Neha Rawat (Retd) : +9893443284
Business Manager,
Electronics and ICT Academy
PDPM Indian Institute of Information Technology,
Design and Manufacturing, Jabalpur,
Dumna Airport Road, Jabalpur 482005
Email: neharawat@iiitdmj.ac.in
Website: ict.iiitdmj.ac.in