RISC-V VLSI Implementation Flow: RTL2GDS
Principal Coordinator:
Joint- Principal Coordinators :
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27 Mar – 10 Apr 2021
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MODULES TOPICS:
- Simulations and Characterization for Libraries
- Design Basics: Circuit, Architecture and System Level
- Constraints and Synthesis : Input Output Constraints, Complex SoC Constraints
- Input Output Files : Lib Files, General files needed in complete flow
- Layer and Power Planning
- Floorplanning
- Delay Calculations and System Implications
- Setup and Hold Discussion
- Placement Basics and Settings
- DRC LVS and Extraction
- Low Power Flow Basics
- Sign Off
- All Modules will be covered using hands on tutorials of RISC-V implementation in open source tool flow.
Registration Fee : (Registration fee to be paid to - E&ICT Academy, Account No. 50302042708, INDIAN BANK, Mehgawan, IIITDM Branch, IFSC Code: IDIB000M694 by NET BANKING/NEFT)
Rs 500/- for academia ( students /faculty/unemployed fresh graduate )
Rs 1000/- for others
Core Team Members, E&ICT Academy:
Prof Aparajita Ojha
Email: aojha@iiitdmj.ac.in
Prof. Vijay Kumar Gupta
Email: vkgupta@iiitdmj.ac.in
Prof. P.N. Kondekar
Email: pnkondekar@iiitdmj.ac.in
Dr. Atul Gupta
Email: atul@iiitdmj.ac.in
Dr. Prashant Kumar Jain
Email: pkjain@iiitdmj.ac.in
Website: ict.iiitdmj.ac.in
Contact us :
Ritu Bhatnagar : +91-8458849734
Business Manager,
Electronics and ICT Academy
PDPM Indian Institute of Information Technology,
Design and Manufacturing, Jabalpur,
Dumna Airport Road, Jabalpur 482005
Email: ritu.bhatnagar@iiitdmj.ac.in
Website: ict.iiitdmj.ac.in